1. Field of the Invention
The present invention relates to systems for modeling and analyzing the behavior of circuits. More specifically, the present invention relates to a method and an apparatus for analyzing inductive effects in a circuit layout.
2. Related Art
Integrated circuits for modern computer systems are constantly being improved to provide computer users with more computing power and increased computing speed. To achieve these improvements, integrated circuit dies are becoming larger and are more densely packed with circuits. Additionally, the speed of the clock signals applied to these circuits is constantly being increased.
As clock speeds continue to increase, it is becoming increasingly important carefully route signal lines (nets) between circuit elements in order to meet timing requirements. After signal lines have been routed between circuit elements, a circuit analysis tool is typically used to model the behavior of the circuit in order to verify that the circuit meets its timing requirements. While tools presently exist to analyze capacitive coupling between various nets within an integrated circuit, and resistive-capacitive (RC) delay through a net, these tools are largely ineffective for circuits operating at today""s high speeds.
One of the reasons for this ineffectiveness is because existing tools do not consider the effects of inductance on the circuit layout. At low clock frequencies, resistance and capacitance are the dominant factors in determining propagation delay through a net on an integrated circuit. However, as clock frequencies increase, inductancexe2x80x94both self-inductance and mutual inductance with neighboring netsxe2x80x94begins to be a significant factor. Failing to account for inductive effects in a high-speed integrated circuit can lead to non-optimal routing, invalid timing margins, and poor performance of the integrated circuit.
Hence, what is needed is a method and an apparatus that considers inductive effects during the process of analyzing noise and propagation delay effect through nets within an integrated circuit.
One embodiment of the present invention provides a system that considers inductive effects while analyzing noise and propagation delay effect in a circuit layout. The system operates by first receiving the circuit layout, wherein the circuit layout specifies a plurality of nets that carry signals between circuit elements. Next, the system converts a given net into a single signal path, which is divided into a number of segments. The system then calculates inductance, capacitance, and resistance values for each segment. Next, the system uses these inductance, capacitance, and resistance values to produce a model for each segment. The system then couples together models for each segment into a model for the given net. The system uses the model for the given net to calculate noise value and to determine a propagation delay effect through the given net.
In a variation on this embodiment, calculating the inductance for a segment involves calculating a self-inductance for the segment and calculating a mutual inductance between the segment and a neighboring segment.
In a further variation, the neighboring segment is a segment from a virtual aggressor net.
In yet a further variation, the virtual aggressor net is a composite of neighboring nets of the target net, which should be analyzed in the circuit layout.
In a variation on this embodiment, inductive effects include inductive noise and/or inductive delay.
In a variation on this embodiment, the number of segments is five.
In a variation on this embodiment, the system combines capacitively coupled noise with inductively coupled noise in determining noise and propagation delay effect through the given net.
In a further variation, combining the capacitively coupled noise with the inductively coupled noise involves adding a fraction of the capacitively coupled noise to a fraction of the inductively coupled noise.